As a low-k film of a semiconductor device, an SiOCH film whose k value (relative permittivity) is about 2.5 to 2.7 has been known.
In a dual damascene method for forming a copper wiring on a low-k film, for example, the following processes are sequentially performed as shown in FIGS. 9A to 9C: forming a underlayer wiring 101 on a substrate 100; depositing a material including Si and C such as an SiCN film 103 as a barrier film such that copper is diffused from the underlayer wiring 101 into an interlayer dielectric 104 which is a low-k film; and depositing the interlayer dielectric 104 thereon. The SiCN film 103 functions as an etch stop film when forming a via-hole 106 in the interlayer dielectric 104.
When forming the via-hole 106 in the interlayer dielectric 104, the composition ratio of the SiCN film 103 is very similar to that of the interlayer dielectric 104. In view of this, the following sequence is used. First, a main etching is performed to roughly etch the interlayer dielectric 104. Then, an over-etching is performed on the interlayer dielectric by converting a process gas into a gas that produces more reaction products. Thus, byproducts are deposited on the bottom of the via-hole 106. By adjusting an amount of the deposits 107 and an amount of active species, an etch rate is decreased to uniformize the depth of the via-hole 106 on the surface. Herein, a part of the byproducts generated by the over-etching is deposited on the bottom of the via-hole 106 as the deposits 107, and the remaining part of the byproducts is vaporized to be discharged together with the process gas.
However, depending on the structure of the device, the surface of the substrate 100 may have dense regions where the gap between the peripheries of the adjacent via-holes 106 is as narrow as, e.g., 0.1 μm, and sparse regions where the above-mentioned gap is as wide as, e.g., 2 μm. If the gap between the adjacent via-holes 106 varies over the surface as above, the total amount of the byproducts does not vary between the respective via-holes 106, but the amount of the byproducts that are vaporized in the via-holes 106 and then remaining on the surface of the wafer W may vary over the surface such that it is greater in the dense regions and smaller in the sparse regions.
The vaporized byproducts are activated by plasma energy, thereby forming the active species that contributes to the etching, and etching the deposits 107 on the bottom of the via-holes 106. Therefore, if the amount of the vaporized byproducts varies over the surface, the amount of the active species is non-uniformly distributed to cause an imbalance in the depths of the via-holes 106. Considering this, if the distribution of the via-holes is not uniform over the surface, the processing conditions including, e.g., a processing temperature, a processing pressure and plasma energy need to be adjusted such that the etching is performed with a uniform depth.
However, depending on the device, there may also exist an extremely sparse region where the gap between the adjacent via-holes 106 is 10 μm or more. In this region, since the amount of active species is very small, the etching process may be stopped in the middle of the process as shown in FIG. 9B. Since the over-etching is performed at a slow rate, an excessively small amount of the active species extremely slows down the etch rate. In this case, the etching process appears to be stopped altogether compared to the other regions where the via-holes 106 are distributed more densely.
Further, if the processing conditions including, e.g., a flow rate of inert gas and/or oxygen gas are adjusted such that the etching is completed in the extremely sparse region where the gap between the adjacent via-holes 106 is very large, the via-hole 106 may be excessively etched to penetrate the SiCN film 103 and reach the underlayer wiring 101 in a region where the via-holes 106 are densely distributed (see FIG. 9C). That is, in forming patterns including the dense region and the extremely sparse region by etching the interlayer dielectric 104, it is very difficult to enhance an etching performance with respect to the via-holes 106 while maintaining a selection ratio suitable for the SiCN film 103.
As a result, in the substrate 100 in which the distribution of the via-holes 106 is very biased, the processing conditions should be strictly controlled such that the depths of the bottom surfaces of all the via-holes 106 are fitted between the top and the bottom surfaces of the SiCN film 103 (i.e., within the depth range where the SiCN film 103 is located). Therefore, the degree of freedom of the processing conditions is significantly limited. In addition, for achieving a more high-layered lamination of the device, it is required to thin the film thickness of the SiCN film 103. In this case, the processing conditions should be more strictly controlled.
The Patent Document 1 discloses a technology in which a negative DC voltage is applied to an upper electrode to increase a selection ratio in etching on an SiOC interface film formed on an SiC film. However, there is no discussion about the substrate 100 in which the via-holes 106 are non-uniformly distributed.
(Patent Document 1) Japanese Patent Application Publication No. 2006-270017 (Paragraphs 0073, 0084, 0173).